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Signal Connections Chapter 3
Lab-PC+ User Manual 3-22 © National Instruments Corporation
and 3-11 illustrate two possible posttrigger data acquisition timing cases. In Figure 3-10, the
rising edge on EXTTRIG is sensed when the EXTCONV* input is high. Thus, the first A/D
conversion occurs on the second falling edge of EXTCONV*, after the rising edge on
EXTTRIG. In Figure 3-11, the rising edge on EXTTRIG is sensed when the EXTCONV* input
is low. In this case, the first A/D conversion occurs on the first falling edge of EXTCONV*,
after the rising edge on EXTTRIG. Notice that Figures 3-10 and 3-11 show a controlled
acquisition mode data acquisition sequence; that is, Sample Counter A1 disables further A/D
conversions after the programmed count (3 in the examples shown in Figures 3-10 and 3-11)
expires. The counter is not loaded with the programmed count until the first falling edge
following a rising edge on the clock input; therefore two extra conversion pulses are generated as
shown in Figures 3-10 and 3-11. EXTTRIG can also be used as an external trigger in freerun
acquisition mode.
t
w
50 nsec minimum
EXTTRIG
EXTCONV*
CONVERT
V
IH
V
IL
t
w
t
w
Sample
Counter
X X321 0
Figure 3-10. Posttrigger Data Acquisition Timing Case 1
t
w
50 nsec minimum
EXTTRIG
V
IH
V
IL
t
w
EXTCONV*
CONVERT
t
d
50 nsec minimum
t
w
Sample
Counter
X 3210
Figure 3-11. Posttrigger Data Acquisition Timing Case 2