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Lab-PC+ User Manual Index-4 © National Instruments Corporation
HWTRIG, 3-21, D-10, E-11, E-13, E-14
INTSCAN, D-14, E-17 to E-19
Lab-PC/PC+, D-7
LDAC0, D-9, E-20 to E-21
LDAC1, 3-23, D-9, E-20 to E-21
MA<2..0>, D-6
OVERFLOW, D-7, E-20. See also A/D
FIFO overflow condition.
OVERRUN, D-8, E-20. See also A/D FIFO
overrun condition.
PRETRIG, 3-21, D-10, E-11, E-12, E-14
SCANEN. See SCANEN bit.
SE/D, D-13
SWTRIG. See SWTRIG bit.
TBSEL, D-9, E-6
TCINTEN, D-11
TWOSCMP, D-6, E-4
board configuration
base I/O address selection, 2-3 to 2-5
DMA channel selection, 2-6 to 2-7
interrupt selection, 2-7 to 2-8
parts locator diagram, 2-2
PC bus interface, 2-1
factory settings (table), 2-3
bus interface specifications, A-6
C
cabling considerations, 3-28
calibration
analog input, 5-3 to 5-6
bipolar input procedure, 5-4 to 5-5
board configuration, 5-4
unipolar input procedure, 5-5 to 5-6
voltage values of ADC input (table), 5-4
analog output, 5-6 to 5-8
bipolar output procedure, 5-6 to 5-7
board configuration, 5-6
unipolar output procedure, 5-8
equipment requirements, 5-1
trimpots, 5-2
location diagram, 5-2
CCLKB1 signal (table), 3-3
channel scanning for multiple A/D
conversions, E-17
channel-scanning cycle, E-17
circuitry. See theory of operation.
circular buffer, E-11
CLK signal. See GATE, CLK, and
OUT signals.
CLKB2 signal (table), 3-3
CNTINT bit
data acquisition timing, 3-24
description, D-7
interrupt programming for analog output
circuitry, E-23
CNTINTEN bit
data acquisition timing, 3-23
description, D-11
interrupt programming for analog output
circuitry, E-23
Command Register 1
channel scanning, E-17
controlled acquisition mode, E-6
posttrigger mode, E-12
pretrigger mode, E-14
description, D-5 to D-6
freerun acquisition mode, E-9
selecting analog input channel, E-3
single-channel interval acquisition
mode, E-19
Command Register 2, D-9 to D-10
Command Register 3
description, D-11 to D-12
digital I/O circuitry programming, E-34
Command Register 4
description, D-13 to D-14
single-channel interval acquisition
mode, E-19
common-mode signal rejection
considerations, 3-12
configuration
analog input, 2-10 to 2-14
DIFF input (four channels), 2-11 to 2-12
input mode, 2-10 to 2-11
input polarity and range, 2-13 to 2-14
jumper settings (table), 2-9
NRSE input (eight channels), 2-13
RSE input (eight channels), 2-12
analog output, 2-9 to 2-10
bipolar output selection, 2-9
jumper settings (table), 2-9
unipolar output selection, 2-10
board
base I/O address selection, 2-3 to 2-5
DMA channel selection, 2-6 to 2-7
interrupt selection, 2-7 to 2-8