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Bus Controller (BC)
8-16
When using fixed wait mode and not using DRAM
(Memory control register 2B B2DRAM = 0, B2WM = 0)
Bit No. Bit name Description Setting conditions
0 DRAM Block 2 DRAM 0: Do not use as DRAM space.
space setting
1 WM Block 2 wait mode 0: fixed wait mode
2 BM Block 2 bus mode 0: Synchronous mode (SYSCLK synchronization)
1: Asynchronous mode (MCLK synchronization)
3 PE Block 2 software page Not using
mode enable
4 BW Block 2 bus width 0: 8 bits
1: 16 bits
7 to 6 ASA1 to 0 AS assert timing 00: 0MCLK
11: 3MCLK
10 to 8 ASN2 to 0 AS negate timing 000: prohibited
Set so that: 001: 1MCLK
ASN ≥ ASA
111: 7MCLK
15 to 11 WEN4 to 0 WE negate timing Settings other than those shown below are prohibited.
Set so that: 00011: 3MCLK
WEN ≥ EA
11111: 31MCLK
~
~
~
~
~
~
Memory control register 2B
Register symbol: MEMCTR2B
Address: x’32000024
Purpose: Sets the bus mode, access timing, etc., for external memory space block 2.
Bit No. 15 14 13 12 11 10 9876543210
Bit B2 B2 B2 B2 B2 B2 B2 B2 B2 B2
–
B2 B2 B2 B2 B2
name WEN4WEN3WEN2WEN1WEN0 ASN2 ASN1 ASN0 ASA1 ASA0 BW PE BM WM
DRAM
Reset 1110101101010000
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W