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Bus Controller (BC)
8-72
Fig. 8-15-3 Bus Arbitration Timing 3
(Bus Authority Release/Bus Authority Acquisition, nfr = 1)
Fig. 8-15-4 Bus Arbitration Timing 4
(Refresh Request Generated While Bus Authority Has Been Released)
MCLK
SYSCLK
“Hi-Z”
An
CSn
“Hi-Z”
RE
“Hi-Z”
WEn
“Hi-Z”
CAS
“Hi-Z”
Dn
“Hi-Z”
BR
BG
CPU
Standby
RASn
“Hi-Z”
External device Bus access
MCLK
SYSCLK
“Hi-Z”
Dn
BR
External device
Refresh
Standby
BG
“Hi-Z”
CSn
“Hi-Z”
RE
“Hi-Z”
WEn
“Hi-Z”
CAS
“Hi-Z”
RASn
“Hi-Z”
An