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Bus Controller (BC)
8-53
(a) Read Timing
Fig. 8-13-24 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and in
Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 4)
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
“Description of Registers.”
(b) Write Timing
AS
CSn
“H”
ADE
BCS
ASA
RWSEL
MCLK
SYSCLK
BCS
A23* to 16
ADM15 to 0
RE
WE0
EA
BCE BCE
ASN
ASA
ADE
ASN
EA
REN
REN
Read low-order side
Read high-order side
A[0]=1A[0]=0
A[0]=0
A[0]=1
“0”( )“L”
data in
data in
: Undefined
: A23 also serves as CS3
*
: Undefined or Hi-Z
“0”( )
“L”
AS
CSn
ASA
ADE
RWSEL
MCLK
SYSCLK
BCS
A23* to 16
ADM15 to 0
RE
WE0
EA
BCE
BCS
BCE
ASN
ASA
ADE
ASN
EA
WEN WEN
“H”
Write low-order side
Write high-order side
A[0]=0 “0”( )“L” A[0]=1
A[0]=1 data outdata outA[0]=0
: Undefined
: A23 also serves as CS3
*
: Undefined or Hi-Z
“0”( )“L”