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Bus Controller (BC)
8-43
Fig. 8-13-14 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and in
Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2)
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
“Description of Registers.”
(a) Read Timing
(b) Write Timing
An
WE0
RE
CS2
MCLK
SYSCLK
D7-0
DK
EA
REN
DW
BCE
“H”
EA
REN
BCE
A[0]=0
DK detection start
A[0]=1
DK detection start
DW
Read low-order side Read high-order side
: Undefined
Consumed internally
by the BC
Consumed internally by the BC
An
WE0
RE
CS2
MCLK
SYSCLK
D7-0
DK
EA
WEN
DW
BCE
“H”
EA
WEN
BCE
A[0]=0
DK detection start
A[0]=1
DK detection start
DW
Write low-order side
Write high-order side
: Undefined
Consumed internally
by the BC
Consumed internally
by the BC