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Bus Controller (BC)
8-71
Fig. 8-15-1 Bus Arbitration Timing 1
(Bus Authority Release/Bus Authority Acquisition, nfr = 4)
Fig. 8-15-2 Bus Arbitration Timing 2
(Bus Authority Release/Bus Authority Acquisition, nfr = 2)
MCLK
SYSCLK
“Hi-Z”
An
CSn
“Hi-Z”
RE
“Hi-Z”
WEn
“Hi-Z”
CAS
“Hi-Z”
Dn
“Hi-Z”
BR
BG
CPU
External device Bus access
Standby
RASn
“Hi-Z”
Standby
MCLK
SYSCLK
“Hi-Z”
An
CSn
“Hi-Z”
RE
“Hi-Z”
WEn
“Hi-Z”
CAS
“Hi-Z”
Dn
“Hi-Z”
BR
BG
CPU
External device
Bus access
RASn
“Hi-Z”