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Bus Controller (BC)
8-36
Fig. 8-13-5 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in
Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2)
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
“Description of Registers.”
Fig. 8-13-6 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in
Address/Data Separate Mode (MCLK = SYSCLK)
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
“Description of Registers.”
An
WEn
RE
CS2
MCLK
SYSCLK
Dn
DK
EA
REN
DW
BCE
Consumed internally by the BC
Read
EA
WEN
DW
BCE
Consumed internally
by the BC
Write
DK detection start
DK detection start
: Undefined
An
WEn
RE
CS2
WEN
MCLK
SYSCLK
Dn
DK
EA
REN
DW
BCE
Consumed internally by the BC
Read
EA
DW
Consumed internally
by the BC
BCE
Write
DK detection start
DK detection start
: Undefined