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Bus Controller (BC)
8-18
After the reset is released, block 2 is set as follows:
Address output end timing 3MCLK
RE negate timing 29MCLK
WE negate timing 29MCLK
RE/WE assert timing 3MCLK
Bus cycle start timing 0MCLK
Bus cycle end timing 31MCLK
AS assert timing 1MCLK
AS negate timing 3MCLK
The bus width is 16 bits, and synchronous fixed wait mode is set.