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Interrupt Controller
9-20
Group 12 interrupt control register
Register symbol: G12ICR
Address: x'34000130
Purpose:
This register is used to enable group 12 interrupts, and to confirm interrupt requests and detection.
Bit No.1514131211109876543210
Bit - G12 G12 G12 - - - IQ1 - - - IQ1 - - - IQ1
name LV2 LV1 LV0 IE IR ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Access R R/W R/W R/W R R R R/W R R R R/W R R R R/W
Bit No. Bit name Description
0 IQ1ID External interrupt 1 interrupt detection flag
0: No interrupt detected 1: Interrupt detected
3 to 1 — "0" is returned when these bits are read.
4 IQ1IR External interrupt 1 interrupt request flag
0: No interrupt request 1: Interrupt request
7 to 5 — "0" is returned when these bits are read.
8 IQ1IE External interrupt 1 interrupt enable flag
0: Disabled 1: Enabled
11 to 9 — "0" is returned when these bits are read.
12 G12LV0 Group 12 interrupt priority level register (LSB)
13 G12LV1 Group 12 interrupt priority level register
14 G12LV2 Group 12 interrupt priority level register (MSB)
Set a level from 6 to 0.
15 — "0" is returned when this bit is read.