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1-4
General Specifications
Clock and
system controller
A/D
10-bit
4 inputs
SIF
UART x 1
multipurpose x 1
synchronous system x 2
ROM
128 KB
(flash memory
256 KB)
Data
RAM
8 KB
32-bit
CPU core
I/O ports
72 pins
(all multipurpose)
Timers
16-bit x 4
8-bit x 12
WDT x 1
Interrupt
controller
38 sources
Bus
controller
includes
DRAM
controller
■ Input ports:
• 4 (all multipurpose)
■ Output ports:
• 15 (all multipurpose)
■ Input/output ports:
• 53 (all multipurpose)
Flash microcontroller specifications
■ Performance identical to that of a mask ROM product guaranteed
■ Overwriting while on board possible through serial communications
■ Batch/block erase possible
Block units 8 KB (multiple blocks can be selected simultaneously)
Package
• LQFP100-P-1414
1.3 Block Diagram
Fig. 1-3-1 MN103001G Block Diagram
* The MN1030F01K (flash version) is equipped with 256 KB of flash memory instead of 128 KB of ROM.