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Bus Controller (BC)
8-9
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Memory control register 0B
Register symbol: MEMCTR0B
Address: x’32000020
Purpose: Sets the bus mode, access timing, etc., for external memory space block 0.
Bit No.1514131211109876543210
Bit B0B0B0B0B0B0B0B0B0B0
–––
B0
––
name WEN4WEN3WEN2WEN1WEN0 ASN2 ASN1 ASN0 ASA1 ASA0 BM
Reset 1 1 1 0 1 0 1 1 0 1 0 0 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W R R
Bit No. Bit name Description Setting conditions
2 BM Block 0 bus mode 0: Synchronous mode (SYSCLK synchronization)
1: Asynchronous mode (MCLK synchronization)
7 to 6 ASA1 to 0 AS assert timing 00: 0MCLK
11: 3MCLK
10 to 8 ASN2 to 0 AS negate timing 000: prohibited
Set so that: 001: 1MCLK
ASN ≥ ASA
111: 7MCLK
15 to 11 WEN4 to 0 WE negate timing Settings other than those shown below are prohibited.
Set so that: 00011: 3MCLK
WEN ≥ EA
11111: 31MCLK
After the reset is released, block 0 is set as follows:
Synchronous mode
Address output end timing 3MCLK
RE negate timing 29MCLK
WE negate timing 29MCLK
RE/WE assert timing 3MCLK
Bus cycle start timing 0MCLK
Bus cycle end timing 31MCLK
AS assert timing 1MCLK
AS negate timing 3MCLK
The bus width is the bus width (8 bits or 16 bits) that accords with the mode specified by the MMOD1 and 0 pins
and the EXMOD1 and 0 pins.
Note: For details on the setting of the MMOD1 and 0 pins and the EXMOD1 and 0 pins, refer to section 8.9,
"Mode Settings."