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Bus Controller (BC)
8-42
(a) Read Timing
(b) Write Timing
Fig. 8-13-13 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and in
Address/Data Separate Mode (MCLK = SYSCLK multiplied by 4)
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
“Description of Registers.”
An
WE0
RE
CSn
MCLK
SYSCLK
D7-0
DK
A[0]=0
EA
REN
DW
DK detection start
BCE
Consumed internally by the BC
A[0]=1
“H”
Read low-order side Read high-order side
EA
REN
DW
DK detection start
BCE
Consumed internally by the BC
: Undefined
An
WE0
RE
CSn
MCLK
SYSCLK
EA
WEN
D7-0
DK
DW
A[0]=0
DK detection start
BCE
EA
WEN
DW
A[0]=1
DK detection start
BCE
“H”
Write low-order side
Write high-order side
: Undefined
Consumed internally
by the BC
Consumed internally
by the BC