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Bus Controller (BC)
8-57
Fig. 8-13-27 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and in Address/
Data Multiplex Mode (MCLK = SYSCLK multiplied by 4)
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
“Description of Registers.”
(b) Write Timing
(a) Read Timing
MCLK
SYSCLK
AS
CSn
ASA
ADE
RWSEL
A23* to 16
ADM15 to 0
RE
WE0
ASN
ASA
ADE
ASN
REN
Read high-order side
Read low-order side
DK
DW
EA
DK detection start
EA
DK detection start
BCE
Consumed internally
by the BC
BCE
REN
A[0]=0
A[0]=1
data in
data in
“H”
A[0]=0
A[0]=1
: Undefined
*
“0” (“L”)
“0” (“L”)
Consumed internally
by the BC
DW
: A23 also serves as CS3
: Undefined or Hi-Z
MCLK
SYSCLK
AS
CSn
ASA
ADE
RWSEL
A23* to 16
ADM15 to 0
RE
WE0
ASN
ASA
ADE
ASN
WEN
Write high-order side
Write low-order side
DK
DW
EA
BCE
Consumed internally
by the BC
Consumed internally
by the BC
BCE
WEN
“H”
DK detection start
DW
EA
DK detection start
A[0]=0
data out
A[0]=0
A[0]=1
data out
A[0]=1
: Undefined
*
“0” (“L”)
“0” (“L”)
Consumed internally
by the BC
: A23 also serves as CS3
: Undefined or Hi-Z