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Bus Controller (BC)
8-17
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When using DRAM (Memory control register 2B B2DRAM = 1 B2WM = 0)
Bit No. Bit name Description Setting conditions
0 DRAM Block 2 DRAM 1: Use as DRAM space
space setting
1 WM Block 2 wait mode 0: fixed wait mode
2 BM Block 2 bus mode 1: Asynchronous mode
(MCLK synchronization)
3 PE Block 2 software page 0: Disable
mode enable 1: Enable
4 BW Block 2 bus width 0: 8 bits
1: 16 bits
7 to 6 ASA1 to 0 Always set 01 Settings other than 01 are prohibited.
10 to 8 ASN2 to 0 RAS precharge cycle 000: prohibited
Use as parameter RP 001: 1MCLK
111: 7MCLK
15 to 11 WEN4 to 0 WE negate timing Settings other than those shown below are prohibited.
Set so that: 00100: 4MCLK
CAO (ADE) + CAS (REN) ≥ WEN 11111: 31MCLK
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When using handshaking mode (Memory control register 2B B2DRAM = 0, B2WM = 1)
Bit No. Bit name Description Setting conditions
0 DRAM Block 2 DRAM 0: Do not use as DRAM space.
space setting
1 WM Block 2 wait mode 1: Handshaking mode
2 BM Block 2 bus mode 0: Synchronous mode (SYSCLK synchronization)
3 PE Block 2 software page Not using
mode enable
4 BW Block 2 bus width 0: 8 bits
1: 16 bits
7 to 6 ASA1 to 0 AS assert timing 00: 0MCLK
11: 3MCLK
10 to 8 ASN2 to 0 AS negate timing 000: prohibited
Set so that: 001: 1MCLK
ASN ≥ ASA
111: 7MCLK
15 to 11 WEN4 to 0 WE negate timing 00000: 0MCLK
11111: 31MCLK