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Bus Controller (BC)
8-70
8.15 Bus Arbitration
In this microcontroller, bus arbitration is implemented through the bus authority request signal (BR) and the bus
authority release signal (BG).
If an external device asserts the BR signal, then once the current bus access that is being executed is completed, the
BG signal is asserted and the bus authority is released to the external device. Once the BR signal is negated, this
LSI negates the BG signal in order to re-acquire the bus authority. However, if a refresh request is generated by the
DRAM control circuit within this microcontroller while the bus authority has been released to an external device,
this LSI negates the BG signal and requests the bus authority back form the external device. The external device
then negates the BR signal in response, and the refresh is executed.
Note that bus arbitration is performed in synchronization with SYSCLK.
Fig. 8-15-1 to 3 show the timing for releasing the bus authority to an external device, and Fig. 8-15-4 shows the
timing when a refresh request is generated while the bus authority has been released. An, CSn, RE, WEn, RASn,
and CAS (and, if there is output on other pins related to the BC, those signals as well) are always output by this
microcontroller which has the bus authority (BG = “H”)*
1
, and go to “Hi-Z” (high impedance) when the bus
authority is released (BG = “L”).
Note that the execution of internal I/O space access requests and external memory space access requests by the
CPU while the bus authority is being released are delayed until the bus authority release is completed.
Accesses which can be executed while the bus authority is being released and accesses which are delayed until bus
authority release is completed are listed below.
(1) Accesses which can be executed while the bus authority is being released
- Internal data RAM space accesses by the CPU
- Internal ROM/internal flash memory space accesses by the CPU
(2) Accesses which are delayed until bus authority release is completed
- Internal I/O space accesses by the CPU
- External memory space accesses by the CPU
Note: For details on pins related to the BC and their statuses, refer to Table 8-5-2, “Operating Status of Pins
Concerning BC.”
*1) However, if a bus access is executed immediately before the bus authority is released to an external device, the
An signal, etc., may go to high impedance, even if BG = “H”, depending on the timing of the completion of that
bus access. Specifically, the An and other signals are placed in the high impedance state at the following
timing relative to the timing at which the BG signal is asserted:
When nfr = 4: Simultaneously, or 1, 2, or 3 MCLK cycles before
When nfr = 2: Simultaneously, or 1 MCLK cycle before
Here, nfr = MCLK frequency/SYSCLK frequency