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Bus Controller (BC)
8-55
(b) Write Timing
Fig. 8-13-26 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and in
Address/Data Multiplex Mode (MCLK = SYSCLK)
For details on the various timing settings, refer to the description of the memory control register in section 8.6,
“Description of Registers.”
(a) Read Timing
A23* to 16
RE
AS
CSn
ADE
ADM15 to 0
ASA
RWSEL
MCLK
SYSCLK
BCS=0
WE0
“H”
BCE BCE
ASN
ADE
ASA
ASN
EA
WEN
EA
WEN
Write low-order side
A[0]=0
A[0]=0
data out
“0”(“L”) A[0]=1
data out
A[0]=1
: Undefined
: A23 also serves as CS3
*
: Undefined or Hi-Z
Write high-order side
“0”(“L”)
A23* to 16
RE
AS
CSn
ADE
ADM15 to 0
ASA
RWSEL
MCLK
SYSCLK
BCS=0
WE0
“H”
BCE BCE
ASN
ADE
ASA
ASN
EA
REN
EA
REN
Read low-order side
Read high-order side
data in
data in
A[0]=0
A[0]=0
A[0]=1
“0” (“L”)
A[0]=1
: Undefined
: A23 also serves as CS3
*
: Undefined or Hi-Z
“0” (“L”)