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2-21
CPU
An even higher interrupt response speed can be realized by assigning only one factor or only a few factors to a
single interrupt level.
Fig. 2-5-6 shows the interrupt sequence flow when assigning one factor to each interrupt level.
Fig. 2-5-6 Interrupt Sequence Flow
[Nested Interrupts]
When a level interrupt occurs, nested interrupts can be prohibited by clearing IE of the PSW. However, nested
interrupts can be achieved even while processing level interrupts by setting IE to "1" during processing. However,
in order for nested interrupts to occur, the interrupts must have a higher priority than interrupt mask level IM2 to
IM0 of the PSW at that time. (The GnICR interrupt priority level LV2 to LV0 is smaller than the PSW interrupt
mask level IM2 to IM0.)
When non-maskable interrupts occur, nesting of level interrupts and non-maskable interrupts is prohibited until the
interrupt handler is finished by execution of the RTI instruction.
[Interrupt Acceptance Timing]
If an interrupt request occurs part-way through the execution of an instruction, even instructions which require
multiple execution cycles such as multiply/divide and other instructions are aborted if possible and the interrupt is
accepted. The aborted instruction is executed again after returning from interrupt processing. Aborting these
instructions sets the interrupt acceptance prohibited interval to 11 cycles or less. (The maximum interrupt prohibited
interval of 11 cycles occurs when saving or restoring all registers with the MOVM, CALL or RET instructions.
This occurs only for special cases such as task context switching.)
3 Cycles
Program
Handler (pre-processing)
Interrupt
max. 11 Cycles
Interrupt processing by hardware
RTI
Interrupt
handler
Handler (post-processing)
1
5
6
Processing for each factor