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Bus Controller (BC)
8-10
8.6.2 Memory Block 1 Control Register
Memory control register 1A/B is used to set the memory block 1 read/write timing, synchronous/asynchronous
mode, DRAM mode, page mode, and bus width through software.
Memory control register 1A
Register symbol: MEMCTR1A
Address: x’32000032
Purpose: Sets the access timing, etc., for external memory space block 1.
Bit No.1514131211109876543210
Bit B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1
name REN4 REN3 REN2 REN1 REN0 BCE4 BCE3 BCE2 BCE1 BCE0 ADE1 ADE0 EA1 EA0 BCS1 BCS0
Reset 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: For the external memory access timing charts, refer to section 8.13, “External Memory Space Access (Non-
DRAM Spaces).”
For the timing charts when using DRAM, refer to section 8.14, “External Memory Space Access (DRAM
Spaces).”
When not using DRAM (Memory control register 1B B1DRAM = 0)
Bit No. Bit name Description Setting conditions
1 to 0 BCS1 to 0 Bus cycle start timing 00: 0MCLK
When
nfr = 2, settings other than “00” or “01” are prohibited. 01: 1MCLK
When
nfr = 1, settings other than “00” are prohibited. 10: 2MCLK
11: 3MCLK
3 to 2 EA1 to 0 RE/WE assert timing 00: 0MCLK
11: 3MCLK
5 to 4 ADE1 to 0 Address output end timing 00: 0MCLK
11: 3MCLK
10 to 6 BCE4 to 0 Bus cycle end timing Settings other than those
Set so that: shown below are prohibited.
BCE ≥ REN, BCE ≥ WEN ≥ EA 00100: 4MCLK
BCE
≥ ASN + ADE
11111: 31MCLK
15 to 11 REN4 to 0 RE negate timing Settings other than those
shown below are prohibited.
00100: 4MCLK
11111: 31MCLK
Note: nfr = MCLK frequency/SYSCLK frequency
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