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Appendix
Appendix-8
* Varies according to the state of the instruction buffer.
Code length
Execution Cycle
Instruction Source Destination Format Remarks
AND AND Dm Dn D0 2 1
AND imm8 Dn D1 3 1
AND imm16 Dn D2 4 1
AND imm32 Dn D4 6 2
AND imm16 PSW D2 4 1
OR OR Dm Dn D0 2 1
OR imm8 Dn D1 3 1
OR imm16 Dn D2 4 1
OR imm32 Dn D4 6 2
OR imm16 PSW D2 4 1
XOR XOR Dm Dn D0 2 1
XOR imm16 Dn D2 4 1
XOR imm32 Dn D4 6 2
NOT NOT Dn D0 2 1
BTST BTST imm8 Dn D1 3 1
BTST imm16 Dn D2 4 1
BTST imm32 Dn D4 6 2
BTST imm8 (d8,An) D2 4 4
BTST imm8 (abs32) D5 7 5
BSET BSET Dm (An) D0 2 5
BSET imm8 (d8,An) D2 4 5
BSET imm8 (abs32) D5 7 6
BCLR BCLR Dm (An) D0 2 5
BCLR imm8 (d8,An) D2 4 5
BCLR imm8 (abs32) D5 7 6
ASR ASR Dm Dn D0 2 1
ASR imm8 Dn D1 3 1
LSR LSR Dm Dn D0 2 1
LSR imm8 Dn D1 3 1
ASL ASL Dm Dn D0 2 1
ASL imm8 Dn D1 3 1
ASL2 ASL2 Dn S0 1 1
ROR ROR Dn D0 2 1
ROL ROL Dn D0 2 1
Bcc BEQ (d8,PC) S1 2 3/1* Branching taken/not taken
BNE (d8,PC) S1 2 3/1* Branching taken/not taken
BGT (d8,PC) S1 2 3/1* Branching taken/not taken
BGE (d8,PC) S1 2 3/1* Branching taken/not taken
BLE (d8,PC) S1 2 3/1* Branching taken/not taken
BLT (d8,PC) S1 2 3/1* Branching taken/not taken
BHI (d8,PC) S1 2 3/1* Branching taken/not taken
BCC (d8,PC) S1 2 3/1* Branching taken/not taken
BLS (d8,PC) S1 2 3/1* Branching taken/not taken
BCS (d8,PC) S1 2 3/1* Branching taken/not taken
BVC (d8,PC) D1 3 4/2* Branching taken/not taken
BVS (d8,PC) D1 3 4/2* Branching taken/not taken
BNC (d8,PC) D1 3 4/2* Branching taken/not taken
BNS (d8,PC) D1 3 4/2* Branching taken/not taken
BRA (d8,PC) S1 2 3 Branching taken
Lcc LEQ S0 1 1/2* Branching taken/not taken
LNE S0 1 1/2* Branching taken/not taken
LGT S0 1 1/2* Branching taken/not taken
LGE S0 1 1/2* Branching taken/not taken
LLE S0 1 1/2* Branching taken/not taken
LLT S0 1 1/2* Branching taken/not taken
LHI S0 1 1/2* Branching taken/not taken
LCC S0 1 1/2* Branching taken/not taken
LLS S0 1 1/2* Branching taken/not taken
LCS S0 1 1/2* Branching taken/not taken
LRA S0 1 1 Branching taken