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CHAPTER 5 CPU ARCHITECTURE
5.1.5 Data memory addressing
The method to specify the address of the instruction to be executed next, or the address of a register or memory
to be manipulated when an instruction is executed is called addressing.
The address of the instruction to be executed next is addressed by the program counter PC (for details, refer to
Section 5.3 Instruction Address Addressing).
On the other hand, concerning addressing of memory which is the object of operations during execution of a
command, in the
µ
PD78058F and
µ
PD78058FY Subseries, abundant addressing modes have been provided in
consideration of operability, etc. Particularly in areas (FB00H to FFFFH) where data memory is incorporated special
addressing which matches the respective functions of the special function register (SFR), general purpose register,
etc., is possible. Figure 5-4 to 5-6 show the data memory addressing modes. For details of each addressing, refer
to Section 5.4 Operand Address Addressing.
Figure 5-4. Data Memory Addressing (
µ
PD78056F, 78056FY)
0000H
General Registers
32 × 8 bits
Internal ROM
49152 × 8 bits
Internal Buffer RAM
32 × 8 bits
External Memory
14976 × 8 bits
Reserved
C000H
BFFFH
FA80H
FA7FH
FAC0H
FABFH
FAE0H
FADFH
FEE0H
FEDFH
FF00H
FEFFH
FFFFH
Internal High-speed RAM
1024 × 8 bits
Reserved
FB00H
FAFFH
FF20H
FF1FH
FE20H
FE1FH
Special Function
Registers (SFRs)
256 × 8 bits
SFR Addressing
Register Addressing
Short Direct
Addressing
Direct Addressing
Register Indirect
Addressing
Based Addressing
Based Indexed
Addressing