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CHAPTER 27 INSTRUCTION SET
Clock Flag
Note 1 Note 2
ZACCY
rp, #word 3 6 – rp ← word
saddrp, #word 4 8 10 (saddrp) ← word
sfrp, #word 4 – 10 sfrp ← word
AX, saddrp 2 6 8 AX ← (saddrp)
saddrp, AX 2 6 8 (saddrp) ← AX
MOVW AX, sfrp 2 – 8 AX ← sfrp
sfrp, AX 2 – 8 sfrp ← AX
AX, rp
Note 3
1 4 – AX ← rp
rp, AX
Note 3
1 4 – rp ← AX
AX, !addr16 3 10 12 + 2n AX ← (addr16)
!addr16, AX 3 10 12 + 2m (addr16) ← AX
XCHW AX, rp
Note 3
1 4 – AX ↔ rp
A, #byte 2 4 – A, CY ← A + byte ×××
saddr, #byte 3 6 8 (saddr), CY ← (saddr) + byte ×××
A, r
Note 4
2 4 – A, CY ← A + r ×××
r, A 2 4 – r, CY ← r + A ×××
A, saddr 2 4 5 A, CY ← A + (saddr) ×××
A, !addr16 3 8 9 + n A, CY ← A + (addr16) ×××
A, [HL] 1 4 5 + n A, CY ← A + (HL) ×××
A, [HL + byte] 2 8 9 + n A, CY ← A + (HL + byte) ×××
A, [HL + B] 2 8 9 + n A, CY ← A + (HL + B) ×××
A, [HL + C] 2 8 9 + n A, CY ← A + (HL + C) ×××
A, #byte 2 4 – A, CY ← A + byte + CY ×××
saddr, #byte 3 6 8 (saddr), CY ← (saddr) + byte + CY ×××
A, r
Note 4
2 4 – A, CY ← A + r + CY ×××
r, A 2 4 – r, CY ← r + A + CY ×××
A, saddr 2 4 5 A, CY ← A + (saddr) + CY ×××
A, !addr16 3 8 9 + n A, CY ← A + (addr16) + CY ×××
A, [HL] 1 4 5 + n A, CY ← A + (HL) + CY ×××
A, [HL + byte] 2 8 9 + n A, CY ← A + (HL + byte) + CY ×××
A, [HL + B] 2 8 9 + n A, CY ← A + (HL + B) + CY ×××
A, [HL + C] 2 8 9 + n A, CY ← A + (HL + C) + CY ×××
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Only when rp = BC, DE or HL
4. Except "r = A"
Remarks 1. One instruction clock is the length of 1 clock cycle of the CPU clock (f
CPU) selected by the processor
clock control register (PCC).
2. This clock cycle applies to internal ROM program.
3. n is the number of waits when external memory expansion area is read from.
4. m is the number of waits when external memory expansion area is written to.
Mnemonic Operands Byte Operation
Instruction
Group
16-bit
data
transfer
ADD
ADDC
8-bit
operation