Filter
Top Products
501
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS
21.4.5 Interrupt request reserve
Among the commands, there are some for which, even if an interrupt request is generated while they are being
executed, reception of the interrupt request is held until execution of the next command is completed. The commands
of this type (interrupt request hold commands) are shown below.
• MOV PSW, #byte
• MOV A, PSW
• MOV PSW, A
• MOV1 PSW.bit, CY
• MOV1 CY, PSW.bit
• AND1 CY, PSW.bit
• OR1 CY, PSW.bit
• XOR1 CY, PSW.bit
• SET1 PSW.bit
• CLR1 PSW.bit
• RETB
• RETI
• PUSH PSW
• POP PSW
• BT PSW.bit, $addr16
• BF PSW.bit, $addr16
• BTCLR PSW.bit, $addr16
•EI
•DI
• Manipulate instructions for IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, PR1L, INTM0, INTM1 registers
Caution The BRK command is not an interrupt request hold command like those above. However, in a
software interrupt that is started by execution of the BRK command, the IE flag is cleared to 0.
Therefore, even if a maskable interrupt is generated during execution of the BRK command, the
interrupt request is not received. However, a non-maskable interrupt request is accepted.
The timing for holding an interrupt request is shown in Figure 21-17.
Figure 21-17. Interrupt Request Hold
Remarks 1. Instruction N: Instruction that holds interrupts requests
2. Instruction M: Instructions other than instruction N
3. The × ×IF (interrupt request) operation does not receive the effect of the value of × ×PR (priority order
level).
CPU processing
× × IF
Instruction N Instruction M
Save PSW and PC,
Jump to interrupt service
Interrupt service
program