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3.2.14 AVSS.............................................................................................................................................. 71
3.2.15 RESET ......................................................................................................................................... 71
3.2.16 X1 and X2 .................................................................................................................................... 71
3.2.17 XT1 and XT2 ................................................................................................................................ 71
3.2.18 V
DD ............................................................................................................................................... 71
3.2.19 V
SS ................................................................................................................................................ 71
3.2.20 VPP (PROM versions only)............................................................................................................ 71
3.2.21 IC (Mask ROM version only) ........................................................................................................ 72
3.3 Input/output Circuits and Recommended Connection of Unused Pins ........................... 73
CHAPTER 4 PIN FUNCTION (
µ
PD78058FY SUBSERIES) ................................................................. 77
4.1 Pin Function List.................................................................................................................... 77
4.1.1 Normal operating mode pins ........................................................................................................ 77
4.1.2 PROM programming mode pins (PROM versions only)............................................................... 82
4.2 Description of Pin Functions ................................................................................................ 83
4.2.1 P00 to P07 (Port 0) ...................................................................................................................... 83
4.2.2 P10 to P17 (Port 1) ...................................................................................................................... 84
4.2.3 P20 to P27 (Port 2) ...................................................................................................................... 84
4.2.4 P30 to P37 (Port 3) ...................................................................................................................... 85
4.2.5 P40 to P47 (Port 4) ...................................................................................................................... 86
4.2.6 P50 to P57 (Port 5) ...................................................................................................................... 86
4.2.7 P60 to P67 (Port 6) ...................................................................................................................... 86
4.2.8 P70 to P72 (Port 7) ...................................................................................................................... 87
4.2.9 P120 to P127 (Port 12) ................................................................................................................ 88
4.2.10 P130 and P131 (Port 13) ............................................................................................................. 88
4.2.11 AV
REF0........................................................................................................................................... 88
4.2.12 AVREF1........................................................................................................................................... 88
4.2.13 AVDD ............................................................................................................................................. 89
4.2.14 AV
SS.............................................................................................................................................. 89
4.2.15 RESET ......................................................................................................................................... 89
4.2.16 X1 and X2 .................................................................................................................................... 89
4.2.17 XT1 and XT2 ................................................................................................................................ 89
4.2.18 V
DD ............................................................................................................................................... 89
4.2.19 VSS ................................................................................................................................................ 89
4.2.20 V
PP (PROM versions only)............................................................................................................ 89
4.2.21 IC (Mask ROM version only) ........................................................................................................ 90
4.3 Input/output Circuits and Recommended Connection of Unused Pins ........................... 91
CHAPTER 5 CPU ARCHITECTURE .....................................................................................................95
5.1 Memory Spaces...................................................................................................................... 95
5.1.1 Internal program memory space .................................................................................................. 98
5.1.2 Internal data memory space......................................................................................................... 99
5.1.3 Special Function Register (SFR) area ......................................................................................... 99
5.1.4 External memory space ............................................................................................................... 99
5.1.5 Data memory addressing ............................................................................................................. 100
5.2 Processor Registers .............................................................................................................. 103