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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS
Main Processing
EI
INTxx
(PR=1)
INTyy
(PR=0)
IE=0
EI
RETI
INTxx
Servicing
INTzz
(PR=0)
IE=0
EI
RETI
INTyy
Servicing
IE=0
RETI
INTzz
Servicing
Figure 21-16. Multiple Interrupt Example (1/2)
Example 1 Example of multiple interrupt requests being generated twice.
During processing of interrupt INTxx, 2 interrupt requests, INTyy and INTzz, are received and multiple
interrupts are generated. Before reception of each interrupt request, the IE command must be issued
and the interrupt request reception permitted status must exist.
Example 2 Example of multiple interrupts not being generated due to priority order control
During processing of interrupt INTxx, interrupt request INTyy was generated, but the priority order
of this interrupt was lower than that of INTxx, so it was not received and multiple interrupts were not
generated. Interrupt request INTyy was held and received after 1 main processing command was
executed.
PR = 0 : High Priority Order Level
PR = 1 : Low Priority Order Level
IE = 0 : Interrupt Request Reception Prohibited
Main Processing INTxx
Servicing
INTyy
Servicing
INTxx
(PR=0)
1 Instruction
Execution
IE=0
INTyy
(PR=1)
EI
IE=0
EI
RETI
RETI