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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS
21.4.2 Maskable Interrupt request reception
For a maskable interrupt request, the interrupt request flag is set at (1) and if the mask (MK) flag of that interrupt
is cleared (0), it is possible for it to be received. A vector interrupt request is received if an interrupt enable state
exists (when the IE flag is set at (1)). However, if a high priority order interrupt is being processed (when the ISP
flag is reset (0)), an interrupt request which has a low priority order specified for it is not received.
The timing from the time when a maskable interrupt request is generated until the interrupt is processed is shown
in Table 21-3.
For the timing of interrupt request reception, see Figures 21-14 and 21-15.
Table 21-3. Times from Maskable Interrupt Request Generation to Interrupt Service
Minimum Time Maximum Time
Note
When ××PR×=0 7 clocks 32 clocks
When ××PR×=1 8 clocks 33 clocks
Note If an interrupt request is generated just before a divide instruction, the wait time is maximized.
Remark 1 clock : (fCPU: CPU clock)
If two or more maskable interrupt requests are generated simultaneously, the request specified for higher priority
with the priority specify flag is acknowledged first. Also, when the priority order specification flag specifies the same
priority order for two interrupts, the interrupt request with the higher default priority order is received first.
Any reserved interrupts request are acknowledged when they become acknowledgeable.
Figure 21-13 shows interrupt request acknowledge processing algorithms.
If a maskable interrupt request is received, the contents of the program status word (PSW) and the program counter
(PC) are saved to the stack in that order, the IE flag is reset (0) and the content of the received interrupt’s priority
order specification flag is saved to the ISP flag. Further, for each interrupt request, data from the predetermined vector
table are loaded to the PC and branched.
Return from the interrupt is possible with the RETI instruction.
fCPU
1