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6
MAJOR REVISIONS IN THIS EDITION
Page Major Revision from Previous Edition
Throughout The following products have already been developed:
µ
PD78056FGC-×××-8BT, 78058FGC-×××-8BT, 78P058FGC-8BT, 78056FYGC-×××-8BT,
78058FYGC-×××-8BT
P133 to The block diagrams of the following ports were changed.
P137, P143 Figures 6-5 and 6-7 P20, P21, P23 to P26 Block Diagram, Figures 6-6 and 6-8 P22 and P27 Block
Diagram, Figure 6-9 P30 to P37 Block Diagram, Figure 6-16 P71 and P72 Block Diagram
P159 Table 7-2 Relationship between CPU Clock and Minimum Instruction Execution Time was added.
P230, P235 Figures 9-10 and 9-13 Square-Wave Output Operation Timing were added.
P295 Note related to operation controls when using the SBI mode of serial interface channel 0 was added.
P297 Note related to BSYE in Figure 16-5 Serial Bus Interface Control Register Format was changed.
P308 Cautions were added to 16.4.3 (2) (a) Bus release signal (REL), and (b) Command signal (CMD)
P435, P436 CSCK was deleted from Figure 19-1 Serial Interface Channel 2 Block Diagram, and Figure 19-2
Baud Rate Generator Block Diagram.
P438 Figure 19-3 Serial Operating Mode Register 2 Format was changed.
P440 Table 19-2 Serial Interface Channel 2 Operating Mode Settings (2) 3-wire serial I/O mode was
changed.
P459 Figure 19-10 Receive Error Timing was changed.
P468 19.4.4 Restrictions on using UART mode was added.
P565 APPENDIX A DIFFERENCES AMONG
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PD78054, 78058F, AND 780058 SUBSERIES was added.
P567 APPENDIX B DEVELOPMENT TOOLS
Overall revision: Contents were adapted to correspond to in-circuit emulators IE-78K0-NS and
IE-78001-R-A
P582 APPENDIX C EMBEDDED SOFTWARE
Overall revision: Fuzzy inference development support system was deleted.
P591 APPENDIX E REVISION HISTORY was added.
The mark shows major revised points.