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CHAPTER 1 OUTLINE (
µ
PD78058F SUBSERIES)
1.7 Block Diagram
Remarks 1. The internal ROM and RAM capacities depend on the product.
2. Pin connection in parentheses is intended for the
µ
PD78P058F.
16-bit TIMER/
EVENT COUNTER
8-bit TIMER/
EVENT COUNTER 1
WATCHDOG TIMER
WATCH TIMER
SERIAL
INTERFACE 0
SERIAL
INTERFACE 1
SERIAL
INTERFACE 2
A/D CONVERTER
D/A CONVERTER
8-bit TIMER/
EVENT COUNTER 2
INTERRUPT
CONTROL
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
V
DD
VSS
IC
(V
PP)
78K/0
CPU CORE
ROM
RAM
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
PORT 12
PORT 13
REAL-TIME
OUTPUT PORT
EXTERNAL
ACCESS
SYSTEM
CONTROL
P00
P01 to P06
P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P72
P120 to P127
P130, P131
RTP0/P120 to
RTP7/P127
AD0/P40 to
AD7/P47
A8/P50 to
A15/P57
RD/P64
WR/P65
WAIT/P66
ASTB/P67
RESET
X1
X2
XT1/P07
XT2
TO0/P30
TI00/INTP0/P00
TI01/INTP1/P01
TO1/P31
TI1/P33
TO2/P32
TI2/P34
SI0/SB0/P25
SO0/SB1/P26
SCK0/P27
SI1/P20
SO1/P21
SCK1/P22
STB/P23
BUSY/P24
SI2/RxD/P70
SO2/TxD/P71
SCK2/ASCK/P72
AVREF0
ANI0/P10 to
ANI7/P17
ANO0/P130,
ANO1/P131
AV
REF1
INTP0/P00 to
INTP6/P06
BUZ/P36
PCL/P35
AV
DD
AV
SS