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CHAPTER 18 SERIAL INTERFACE CHANNEL 1
SCK1
SO1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
CSIIF1
TRF
SI1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Interval
(3) Communication operation
(a) Basic transmission/reception mode
This transmission/reception mode is the same as the 3-wire serial I/O mode in which specified number
of data are transmitted/received in 8-bit units.
Serial transmission is started by writing the desired data to serial I/O shift register 1 (SIO1) when bit 7
(CSIE1) of serial operation mode register 1 (CSIM1) is set at 1.
When the final byte has been sent, an interrupt request flag (CSIIF1) is set. However, judge the termination
of auto send and receive, not by CSIIF1 (interrupt request flag) but by bit 3 (TRF) of the auto data send
and receive control register (ADTC).
If busy control and strobe control are not executed, the P23/STB and P24/BUSY pins can be used as
normal input/output ports.
Figure 18-8 shows the basic transmission/reception mode operation timings, and Figure 18-9 shows the
operation flowchart. Figure 18-10 shows the operation of the internal buffer RAM when 6 bytes of data
are transmitted or received.
Figure 18-8. Basic Transmission/Reception Mode Operation Timings
Cautions 1. Because, in the basic transmission/reception mode, the automatic transmit/receive
function writes/reads data to/from the internal buffer RAM after 1-byte transmission/
reception, an interval is inserted till the next transmission/reception. As the internal
buffer RAM write/read is performed at the same time as CPU processing, the
maximum interval is dependent upon CPU processing and the value of the automatic
data transmit/receive interval specify register (ADTI) (see (5) "Automatic transmit/
receive interval time").
2. When TRF is cleared, the SO1 pin becomes low level.
CSIIF1: Interrupt request flag
TRF : Bit 3 of the auto data send and receive control register (ADTC)