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LIST OF FIGURES (7/8)
Figure No. Title Page
20-4 Real-time Output Port Mode Register Format .................................................................................. 474
20-5 Real-time Output Port Control Register Format................................................................................ 475
21-1 Basic Configuration of Interrupt Function ......................................................................................... 480
21-2 Interrupt Request Flag Register Format ........................................................................................... 483
21-3 Interrupt Mask Flag Register Format ................................................................................................ 484
21-4 Priority Specify Flag Register Format ............................................................................................... 485
21-5 External Interrupt Mode Register 0 Format ...................................................................................... 486
21-6 External Interrupt Mode Register 1 Format ...................................................................................... 487
21-7 Sampling Clock Select Register Format ........................................................................................... 488
21-8 Noise Elimination Circuit Input/Output Timing (During Rising Edge Detection) ................................ 489
21-9 Program Status Word Format ........................................................................................................... 490
21-10 Flowchart from the Time a Non-maskable Interrupt Request Is Generated Until It Is Received ...... 492
21-11 Non-Maskable Interrupt Request Acknowledge Timing .................................................................... 492
21-12 Non-Maskable Interrupt Request Acknowledge Operation ............................................................... 493
21-13 Interrupt Request Acknowledge Processing Algorithm ..................................................................... 495
21-14 Interrupt Request Acknowledge Timing (Minimum Time) ................................................................. 496
21-15 Interrupt Request Acknowledge Timing (Maximum Time) ................................................................ 496
21-16 Multiple Interrupt Example ................................................................................................................ 499
21-17 Interrupt Request Hold...................................................................................................................... 501
21-18 Basic Configuration of Test Function ................................................................................................ 502
21-19 Format of Interrupt Request Flag Register 1L .................................................................................. 503
21-20 Format of Interrupt Mask Flag Register 1L ....................................................................................... 503
21-21 Key Return Mode Register Format ................................................................................................... 504
22-1 Memory Map When Using External Device Expansion Function ..................................................... 506
22-2 Memory Expansion Mode Register Format ...................................................................................... 508
22-3 Memory Size Switching Register Format.......................................................................................... 509
22-4 Instruction Fetch from External Memory ........................................................................................... 511
22-5 External Memory Read Timing ......................................................................................................... 512
22-6 External Memory Write Timing .......................................................................................................... 513
22-7 External Memory Read Modify Write Timing..................................................................................... 514
23-1 Oscillation Stabilization Time Select Register Format ...................................................................... 516
23-2 HALT Mode Clear upon Interrupt Request Generation ..................................................................... 518
23-3 HALT Mode Release by RESET Input .............................................................................................. 519
23-4 STOP Mode Release by Interrupt Request Generation.................................................................... 521
23-5 Release by STOP Mode RESET Input ............................................................................................. 522
24-1 Block Diagram of Reset Function ..................................................................................................... 523
24-2 Timing of Reset Input by RESET Input ............................................................................................. 524
24-3 Timing of Reset due to Watchdog Timer Overflow............................................................................ 524
24-4 Timing of Reset Input in STOP Mode by RESET Input..................................................................... 524