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LIST OF FIGURES (2/8)
Figure No. Title Page
7-4 Oscillation Mode Selection Register Format ..................................................................................... 159
7-5 Main System Clock Waveform due to Writing to OSMS ................................................................... 160
7-6 External Circuit of Main System Clock Oscillator .............................................................................. 161
7-7 External Circuit of Subsystem Clock Oscillator ................................................................................. 162
7-8 Examples of Resonator with Incorrect Connection ........................................................................... 162
7-9 Main System Clock Stop Function .................................................................................................... 166
7-10 System Clock and CPU Clock Switching .......................................................................................... 169
8-1 16-Bit Timer/Event Counter Block Diagram ...................................................................................... 175
8-2 16-Bit Timer/Event Counter Output Control Circuit Block Diagram .................................................. 176
8-3 Timer Clock Selection Register 0 Format ......................................................................................... 179
8-4 16-Bit Timer Mode Control Register Format ..................................................................................... 181
8-5 Capture/Compare Control Register 0 Format ................................................................................... 182
8-6 16-Bit Timer Output Control Register Format ................................................................................... 183
8-7 Port Mode Register 3 Format ........................................................................................................... 184
8-8 External Interrupt Mode Register 0 Format ...................................................................................... 185
8-9 Sampling Clock Select Register Format ........................................................................................... 186
8-10 Control Register Settings for Interval Timer Operation ..................................................................... 187
8-11 Interval Timer Configuration Diagram ............................................................................................... 188
8-12 Interval Timer Operation Timings ...................................................................................................... 188
8-13 Control Register Settings for PWM Output Operation ...................................................................... 190
8-14 Example of D/A Converter Configuration with PWM Output ............................................................. 191
8-15 TV Tuner Application Circuit Example .............................................................................................. 191
8-16 Control Register Settings for PPG Output Operation ....................................................................... 192
8-17 Control Register Settings for Pulse Width Measurement with Free-Running Counter and
One Capture Register ....................................................................................................................... 193
8-18 Configuration Diagram for Pulse Width Measurement by Free-Running Counter ............................ 194
8-19 Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture
Register (with Both Edges Specified) ............................................................................................... 194
8-20 Control Register Settings for Two Pulse Width Measurements with Free-Running Counter ............ 195
8-21 Timing of Pulse Width Measurement Operation with Free-Running Counter
(with Both Edges Specified) .............................................................................................................. 196
8-22 Control Register Settings for Pulse Width Measurement with Free-Running Counter and
Two Capture Registers ..................................................................................................................... 197
8-23 Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture
Registers (with Rising Edge Specified) ............................................................................................. 198
8-24 Control Register Settings for Pulse Width Measurement by Means of Restart ................................ 199
8-25 Timing of Pulse Width Measurement Operation by Means of Restart
(with Rising Edge Specified) ............................................................................................................. 199
8-26 Control Register Settings in External Event Counter Mode .............................................................. 200
8-27 External Event Counter Configuration Diagram................................................................................ 201
8-28 External Event Counter Operation Timings (with Rising Edge Specified) ........................................ 201
8-29 Control Register Settings in Square-Wave Output Mode ................................................................. 202
8-30 Square-Wave Output Operation Timing ............................................................................................ 203