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CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT
CLOE
7
TCL06
6
TCL05 TCL04
4
TCL03
3210
FF40H
Address
TCL0
Symbol
TCL02 TCL01 TCL00
5
00H
After
Reset
R/W
R/W
0
0
0
0
1
1
1
1
1
Other than above
0
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
TCL03 TCL02 TCL01
f
XT
(32.768 kHz)
f
XX
f
XX
/2
f
XX
/2
2
f
XX
/2
3
f
XX
/2
4
f
XX
/2
5
f
XX
/2
6
f
XX
/2
7
Setting prohibited
f
X
(5.0 MHz)
f
X
/2 (2.5 MHz)
f
X
/2
2
(1.25 MHz)
f
X
/2
3
(625 kHz)
f
X
/2
4
(313 kHz)
f
X
/2
5
(156 kHz)
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
f
X
/2 (2.5 MHz)
f
X
/2
2
(1.25 MHz)
f
X
/2
3
(625 kHz)
f
X
/2
4
(313 kHz)
f
X
/2
5
(156 kHz)
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
f
X
/2
8
(19.5 kHz)
PCL Output Clock Selection
CLOE
0
1
Output disable
Output enable
0
0
0
0
1
1
Other than above
0
0
1
1
0
1
0
1
0
1
0
1
TCL06 TCL05 TCL04
TI00 (Valid edge specifiable)
2f
XX
f
XX
f
XX
/2
f
XX
/2
2
Watch Timer Output (INTTM3)
Setting prohibited
Setting prohibited
f
X
(5.0 MHz)
f
X
/2 (2.5 MHz)
f
X
/2
2
(1.25 MHz)
f
X
(5.0 MHz)
f
X
/2 (2.5 MHz)
f
X
/2
2
(1.25 MHz)
f
X
/2
3
(625 kHz)
16-Bit Timer Register Count Clock Selection
TCL00
0
1
0
1
0
1
0
1
0
MCS = 1 MCS = 0
MCS = 1 MCS = 0
PCL Output Control
Figure 12-3. Timer Clock Select Register 0 Format
Cautions 1. The valid edge of pin TI00/P00/INTP0 is set with the external mode register 0 (INTM0).
Also, the frequency of the sampling clock is selected with the sampling clock selection
register (SCS).
2. When enabling PCL output, set TCL00 to TCL03, then set 1 in CLOE with a 1-bit memory
manipulation instruction.
3. To read the count value when TI00 has been specified as the TM0 count clock, the value
should be read from TM0, not from 16-bit capture/compare register 01 (CR01).
4. When rewriting TCL0 to other data, stop the clock operation beforehand.