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LIST OF FIGURES (6/8)
Figure No. Title Page
18-5 Automatic Data Transmit/Receive Interval Specify Register Format ................................................ 395
18-6 3-Wire Serial I/O Mode Timings ........................................................................................................ 401
18-7 Circuit of Switching in Transfer Bit Order .......................................................................................... 402
18-8 Basic Transmission/Reception Mode Operation Timings ................................................................. 411
18-9 Basic Transmission/Reception Mode Flowchart ............................................................................... 412
18-10 Internal Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive
Mode) ................................................................................................................................................ 413
18-11 Basic Transmission Mode Operation Timings................................................................................... 415
18-12 Basic Transmission Mode Flowchart ................................................................................................ 416
18-13 Internal Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) ........................... 417
18-14 Repeat Transmission Mode Operation Timing.................................................................................. 419
18-15 Repeat Transmission Mode Flowchart ............................................................................................. 420
18-16 Internal Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode)......................... 421
18-17 Automatic Transmission/Reception Suspension and Restart ........................................................... 423
18-18 System Configuration When the Busy Control Option Is Used......................................................... 424
18-19 Operation Timings When Using Busy Control Option (BUSY0 = 0).................................................. 425
18-20 Busy Signal and Wait Cancel (When BUSY0 = 0) ............................................................................ 426
18-21 Operation Timings When Using Busy & Strobe Control Option (BUSY0 = 0)................................... 427
18-22 Operation Timing of the Bit Slippage Detection Function Through the Busy Signal
(When BUSY0 = 1) ........................................................................................................................... 428
18-23 Automatic Transmit/Receive Interval Time ....................................................................................... 429
18-24 Operation Timing with Automatic Data Transmit/Receive Function Performed by Internal Clock .... 430
19-1 Serial Interface Channel 2 Block Diagram ........................................................................................ 435
19-2 Baud Rate Generator Block Diagram ............................................................................................... 436
19-3 Serial Operating Mode Register 2 Format ........................................................................................ 438
19-4 Asynchronous Serial Interface Mode Register Format ..................................................................... 439
19-5 Asynchronous Serial Interface Status Register Format .................................................................... 441
19-6 Baud Rate Generator Control Register Format ................................................................................ 442
19-7 Asynchronous Serial Interface Transmit/Receive Data Format ........................................................ 455
19-8 Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing ..... 457
19-9 Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing .......... 458
19-10 Receive Error Timing ........................................................................................................................ 459
19-11 Receive Buffer Register (RXB) Status and Receive Completion Interrupt Request (INTSR)
Generation When Receiving Is Terminated ...................................................................................... 460
19-12 3-Wire Serial I/O Mode Timing .......................................................................................................... 466
19-13 Circuit of Switching in Transfer Bit Order .......................................................................................... 467
19-14 Receive Completion Interrupt Request Generation Timing (When ISRM = 1).................................. 468
19-15 Period that Reading Receive Buffer Register Is Prohibited .............................................................. 469
20-1 Real-time Output Port Block Diagram............................................................................................... 472
20-2 Real-time Output Buffer Register Configuration ............................................................................... 473
20-3 Port Mode Register 12 Format ......................................................................................................... 474