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CHAPTER 21 INTERRUPT AND TEST FUNCTIONS
21.4.3 Software interrupt request acknowledge operation
A software interrupt request is received by the execution of a BRK command. A software interrupt cannot be
prohibited.
If a software interrupt request is received, the contents of the program status word (PSW) and the program counter
(PC) are saved to the stack in that order, the IE flag is reset (0) and the contents of the vector table (003EH, 003FH)
are loaded in the PC and branched.
Return from the software interrupt is possible with the RETB instruction.
Caution Do not use the RETI instruction for returning from the software interrupt.
21.4.4 Multiple interrupt servicing
During interrupt processing, the capacity to receive other distinct interrupt requests is called multiple interrupts.
Multiple interrupts are not generated (except for nonmaskable interrupts) unless reception of an interrupt request
is permitted (IE = 1). Also, at the point when an interrupt request is received, further reception of an interrupt request
is prohibited (IE = 0). Therefore, to permit multiple interrupts, it is necessary to set the IE flag at (1) by the IE command
during interrupt processing and permit interrupt reception.
Also, even if interrupt reception is permitted, there are some cases where multiple interrupts are not permitted,
but that is controlled by the interrupts’ priority order. There are two types of interrupt priority order, the default priority
order and the programmable priority order, but control of multiple interrupts is controlled by programmable priority
order.
In the interrupt permitted state, if an interrupt request is generated with the same level as, or a higher level of priority
order than the interrupt currently being processed, it is received as a multiple interrupt. If an interrupt request with
a lower priority order than the interrupt currently being processed is generated, it is not received as a multiple interrupt.
An interrupt request generated while interrupts are prohibited, or when multiple interrupts are not permitted due
to the interrupt request’s low priority order, is held. Then, when the interrupt processing currently in progress is
completed, the interrupt request is received after 1 main processing command has been executed.
Furthermore, multiple interrupts are not permitted during processing of a nonmaskable interrupt.
Table 21-4 shows interrupt requests which can be multiple interrupts and Figure 21-16 shows a multiple interrupt
example.