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114 AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions
33234H
5.5.2.7 Performance Event Counter 0 Select MSR (PERF_SEL0_MSR
5.5.2.8 Performance Event Counter 1 Select MSR (PERF_SEL1_MSR)
MSR Address 00000186h
Typ e R /W
Reset Value 00000000_00000000h
PERF_SEL0_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
RSVD
PC_EN
RSVD PC0_UMASK PC0_EVENT
PERF_SEL0_MSR Bit Descriptions
Bit Name Description
63:23 RSVD Reserved. Write as read.
22 PC_EN Performance Event Counters 0 and 1 Enable.
0: Disable counters.
1: Enable counters.
21:16 RSVD Reserved. Write as read.
15:8 PC0_UMASK Performance Event Counter 0 Unit Mask. Selects sub-events.
00h: All sub-events counted.
7:0 PC0_EVENT Performance Event Counter 0 Event Select Value. See individual module chapters for
performance event selections.
MSR Address 00000187h
Typ e R /W
Reset Value 00000000_00000000h
PERF_SEL1_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
RSVD PC1_UMASK PC1_EVENT
PERF_SEL1_MSR Bit Descriptions
Bit Name Description
63:16 RSVD Reserved. Write as read.
15:8 PC1_UMASK Performance Event Counter 1 Unit Mask. Selects sub-events.
00h: All sub-events counted.
7:0 PC1_EVENT Performance Event Counter 1 Event Select Value. See individual module chapters for
performance event selections.