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AMD Geode™ LX Processors Data Book 127
CPU Core Register Descriptions
33234H
5.5.2.18 XC Microcode Address MSR (XC_UADDR_MSR)
5.5.2.19 ID Configuration MSR (ID_CONFIG_MSR)
MSR Address 00001213h
Typ e RO
Reset Value 00000000_00000000h
XC_UADDR_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD UADDR4 UADDR3 UADDR2[11:8]
313029282726252423222120191817161514131211109876543210
UADDR2[7:0] UADDR1 UADDR0
XC_UADDR_MSR Bit Descriptions
Bit Name Description
63:60 RSVD Reserved.
59:48 UADDR4 Microcode Address for Exception 4.
47:36 UADDR3 Microcode Address for Exception 3.
35:24 UADDR2 Microcode Address for Exception 2.
23:12 UADDR1 Microcode Address for Exception 1.
11:0 UADDR0 Microcode Address for Exception 0. Most recent exception.
MSR Address 00001250h
Typ e R /W
Reset Value 00000000_00000002h
ID_CONFIG_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
RSVD
GPF_TR
INV_3DNOW
SERIAL
ID_CONFIG_MSR Bit Descriptions
Bit Name Description
63:3 RSVD (RO) Reserved (Read Only).
2GPF_TR General Protection Faults on Test Register Accesses. Generate general protection
faults on accesses to Test Registers.
0: Disable. (Default)
1: Enable.
1 INV_3DNOW Inverse 3DNow!™. Inverse AMD 3DNow!™ instructions PFRCPV and RFRSQRTV.
0: Disable.
1: Enable. (Default)
0 SERIAL Serialize. Serialize the CPU integer pipeline by only allowing one instruction in the pipe-
line at a time.
0: Integer pipeline is not serialized. (Default)
1: Integer pipeline is serialized.