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328 AMD Geode™ LX Processors Data Book
Display Controller Register Descriptions
33234H
6.6.5.1 DC Horizontal and Total Timing (DC_H_ACTIVE_TIMING)
This register contains horizontal active and total timing information.
DC Memory Offset 040h
Typ e R /W
Reset Value xxxxxxxxh
DC_H_ACTIVE_TIMING Register Map
313029282726252423222120191817161514131211109876543210
RSVD H_TOTAL RSVD H_ACTIVE
DC_H_ACTIVE_TIMING Bit Descriptions
Bit Name Description
31:28 RSVD Reserved. These bits should be programmed to zero.
27:16 H_TOTAL Horizontal Total. This field represents the total number of pixel clocks for a given scan
line minus 1. Note that the value must represent a value greater than the H_ACTIVE field
(bits [11:0]) because it includes border pixels and blanked pixels. For flat panels, this
value will never change. Unlike previous versions of the DC, the horizontal total can be
programmed to any pixel granularity; it is not limited to character (8-pixel) granularity.
15:12 RSVD Reserved. These bits should be programmed to zero.
11:0 H_ACTIVE Horizontal Active. This field represents the total number of pixel clocks for the displayed
portion of a scan line minus 1. Note that for flat panels, if this value is less than the panel
active horizontal resolution (H_PANEL), the parameters H_BLK_START, H_BLK_END
(DC Memory Offset 044h[11:0, 27:16]), H_SYNC_ST, and H_SYNC_END (DC Memory
Offset 048h[11:0, 27:16]) should be reduced by the value of H_ADJUST (or the value of
H_PANEL - H_ACTIVE / 2) to achieve horizontal centering.
Unlike previous versions of the DC, this field can be programmed to any pixel granularity;
it is not limited to character (8-pixel) granularity.
If graphics scaling is enabled, this value represents the width of the final (scaled) image
to be displayed. The width of the frame buffer image may be different in this case;
DC_FB_ACTIVE (DC Memory Offset 05Ch) is used to program the horizontal and verti-
cal active values in the frame buffer when graphics scaling is enabled.
H_ACTIVE must be set to at least 64 pixels.