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548 AMD Geode™ LX Processors Data Book
GeodeLink™ Control Processor Register Descriptions
33234H
6.14.2.5 GLCP Debug Output from Chip (GLCP_DBGOUT)
This register is reserved for internal use by AMD and should not be written to.
6.14.2.6 GLCP Processor Status (GLCP_PROCSTAT)
Note that the names of these bits have the read status data before the "_" and the write behavior after it.
MSR Address 4C00000Ch
Typ e R /W
Reset Value 00000000 00000000h
MSR Address 4C00000Dh
Typ e R /W
Reset Value Bootstrap Dependant
GLCP_PROCSTAT Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
RSVD
RESET_NONE
STOPCLK_NONE
GLACT_UNSTALL
GLCPSTALL_DMI
STALL_SMI
SUSP_STOPCLK
DMI_STALL
GLCP_PROCSTAT Bit Descriptions
Bit Name Description
63:7 RSVD Reserved. Writing these bits has no effect.
6 RESET_NONE Reset Status. When read, this bit is high if a hard or soft reset to the
AMD Geode™ LX processor has occurred since this register was last read. Writing
this bit has no effect.
5 STOPCLK_ NONE Stop Clock Status. When read, this bit is high if a GLCP stop clock action has
occurred since this register was last read. Writing this bit has no effect.
4 GLACT_UNSTALL GLIU1 Debug Action Status. When read, this bit is high if the GLCP has triggered
a GLIU1 debug action since this register was last read. Writing this bit high unstalls
the processor.
3 GLCPSTALL_ DMI GLCP Stall Status. When read, this bit is high if the GLCP is stalling the CPU.
Writing this bit high causes a GLCP DMI to the processor.
2 STALL_ SMI CPU Stall Status. When read, this bit is high if the CPU is stalled for any reason.
Writing this bit high causes a GLCP SMI to the processor. Bit 1 of GLD_MSR_SMI
(MSR 4C000002h) gets set by this SMI and an SMI is triggered, assuming appro-
priate SMI enable settings.
1 SUSP_ STOPCLK CPU Suspended Stop Clock Status. When read, this bit is high if the CPU has
suspended execution for any reason since this register was last read. Writing this
bit high causes the GLCP to stop all clocks identified in GLCP_CLKDISABLE
(MSR 4C000012h).
0DMI_STALL CPU DMI Stall Status. When read, this bit is high if the CPU is in DMI mode. Writ-
ing this bit high causes the GLCP to “DEBUG_STALL” the processor.