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AMD Geode™ LX Processors Data Book 545
GeodeLink™ Control Processor Register Descriptions
33234H
6.14.2 GLCP Specific MSRs - GLCP Control MSRs
6.14.2.1 GLCP Clock Disable Delay Value (GLCP_CLK_DIS_DELAY)
6.14.2.2 GLCP Clock Mask for Sleep Request (GLCP_PMCLKDISABLE)
MSR Address 4C000008h
Typ e R /W
Reset Value 00000000_00000000h
GLCP_CLK_DIS_DELAY Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
RSVD CLK_DELAY
GLCP_CLK_DIS_DELAY Bit Descriptions
Bit Name Description
63:24 RSVD Reserved. Write as read.
23:0 CLK_DELAY Clock Disable Delay. If enabled in GLCP_GLB_PM (CLK_DLY_EN bit, MSR
4C00000Bh[4] = 1), indicates the period to wait from SLEEP_REQ before gating off
clocks specified in GLCP_PMCLKDISABLE (MSR 4C000009h). If this delay is enabled,
it overrides or disables the function of GLCP_CLK4ACK (MSR 4C000013h). If the
CLK_DLY_EN bit is not set, but this register is non-zero, then this register serves as a
timeout for the CLK4ACK behavior.
MSR Address 4C000009h
Typ e R /W
Reset Value 00000000_00000000h
GLCP_PMCLKDISABLE Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
VIPVIP
VIPGLIU
313029282726252423222120191817161514131211109876543210
AES
AESGLIU
AESEE
GLCPDBG
GLCPGLIU
GLCPPCI
VPVOP
VPDOT_2
VPDOT_1
VPDOT_0
VPGLIU_1
VPGLIU_0
PCIPCIF
PCIPCI
PCIGLIU
GLIU1_1
GLIU1_0
DCGLIU_1
DCGLIU_0
RSVD
DCDOT_0
GLIU0_1
GLIU0_0
GP
GLMC
DRAM
BC_GLIU
BC_VA
MSS
IPIPE
FPUFAST
FPUSLOW
GLCP_PMCLKDISABLE Bit Descriptions
Bit Name Description
63:34 RSVD Reserved.
33 VIPVIP VIP VIPCLK Off. When set, disables VIP VIPCLK.
32 VIPGLIU VIP GLIU Clock Off. When set, disables VIP GLIU clock.
31 AES AES Core Functional Clock Off. When set, disables AES encryption/decryption
clock.
30 AESGLIU AES GLIU Clock Off. When set, disables AES GLIU interface clock.
29 AESEE AES EEPROM Clock Off. When set, disables AES EEPROM clock.