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74 AMD Geode™ LX Processors Data Book
GLIU Register Descriptions
33234H
4.2.3.4 Request Compare Value (RQ_COMPARE_VAL[0:3]
The RQ Compare Value and the RQ Compare Mask enable traps on specific transactions. A hit to the RQ Compare is
determined by hit = (RQ_IN & RQ_COMPARE_MASK) == RQ_COMPARE_VAL). A hit can trigger the RQ_CMP error
sources when they are enabled. The value is compared only after the packet is arbitrated.
Request Compare Value (RQ_COMPARE_VAL[0])
Request Compare Value (RQ_COMPARE_VAL[1])
Request Compare Value (RQ_COMPARE_VAL[2])
Request Compare Value (RQ_COMPARE_VAL[3])
2 HIT_ASMI Assert ASMI on Descriptor Hit. The descriptor hits are ANDed with the masks and then
all ORed together.
0: Disable.
1: Enable.
1HIT_DEC Decrement Counter on Descriptor Hit. The descriptor hits are ANDed with the masks
and then all ORed together.
0: Disable.
1: Enable.
0HIT_LDEN Load Counter on Descriptor Hit. The descriptor hits are ANDed with the masks and
then all ORed together.
0: Disable.
1: Enable.
STATISTIC_ACTION[0:3] Bit Descriptions
Bit Name Description
MSR Address GLIU0: 100000C0h
GLIU1: 400000C0h
Typ e R /W
Reset Value 001FFFFF_FFFFFFFFh
MSR Address GLIU0: 100000C2h
GLIU1: 400000C2h
Typ e R /W
Reset Value 001FFFFF_FFFFFFFFh
MSR Address GLIU0: 100000C4h
GLIU1: 400000C4h
Type R /W
Reset Value 001FFFFF_FFFFFFFFh
MSR Address GLIU0: 100000C6h
GLIU1: 400000C6h
Type R /W
Reset Value 001FFFFF_FFFFFFFFh
RQ_COMPARE_VAL[0:3] Register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD RQ_VAL
313029282726252423222120191817161514131211109876543210
RQ_VAL
RQ_COMPARE_VAL[0:3] Bit Descriptions
Bit Name Description
63:53 RSVD Reserved.
52:0 RQ_VAL Request Packet Value. This is the value compared against the logical bit-wise AND of
the incoming request packet and the RQ_COMPMASK in order to determine a ‘hit”.