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AMD Geode™ LX Processors Data Book 619
8
Instruction Set 33234H
8.0Instruction Set
This chapter provides the general instruction set format and detailed information on the AMD Geode™ LX processor’s
instructions/instruction encodings. The instruction set is divided into three categories:
• CPUID Instruction Set - listed in Section 8.2 on page 627.
• Processor Core Instruction Set - listed in Section 8.3 on page 633.
• MMX™, FPU, and AMD 3DNow!™ Instruction Sets (including extensions) - listed in Section 8.4 on page 658.
In the above listed sections are tables that provide information on the instruction encoding, and the instruction clock counts
for each instruction. The clock count values for these tables are based on the following assumptions:
1) All clock counts refer to the internal processor core clock frequency.
2) The instruction has been prefetched, decoded, and is ready for execution.
3) Any needed memory operands are in the cache in the last accessed way (i.e., Way0, Way1, Way2, or Way3). Add two
clocks if not in last accessed way.
4) No exceptions are detected during instruction execution.
5) If an effective address is calculated, it does not use two general register components. One register, scaling, and a dis-
placement value can be used within the clock count shown. However, if the effective address calculation uses a base
register, an index register, and a displacement value, a cycle must be added to the count.
6) All clock counts assume an 8-byte span of 32-bit memory/IO operands.
7) If instructions access a 32-bit operand not within an 8-byte block, add one clock for read or write and add two clocks for
read and write.
8) For non-cached memory accesses, add several clocks. Cache miss accesses are approximately an additional 25
clocks, the exact number depends upon the cycle/operation running.
9) Locked cycles are not cacheable. Therefore, using the LOCK prefix with an instruction adds additional clocks as spec-
ified in item 8 above.
8.1 General Instruction Set Format
Depending on the instruction, the AMD Geode LX processor core instructions follow the general instruction format shown in
Table 8-1. These instructions vary in length and can start at any byte address. An instruction consists of one or more bytes
that can include prefix bytes, at least one opcode byte, a mod r/m byte, an s-i-b byte, address displacement, and immedi-
ate data. An instruction can be as short as one byte and as long as 15 bytes. If there are more than 15 bytes in the instruc-
tion, a general protection fault (error code 0) is generated.
The fields in the general instruction format at the byte level are summarized in Table 8-2 on page 620 and detailed in the fol-
lowing subsections.
Table 8-1. General Instruction Set Format
Prefix (Optional) Opcode
Register and Address Mode Specifier
Address
Displacement
Immediate
Data
mod r/m Byte s-i-b Byte
mod reg r/m ss index base
0 or More Bytes 1 or 2 Bytes 7:6 5:3 2:0 7:6 5:3 2:0 0, 8, 16, or 32 Bits 0, 8, 16, or 32 Bits