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AMD Geode™ LX Processors Data Book 75
GLIU Register Descriptions
33234H
4.2.3.5 Request Compare Mask (RQ_COMPARE_MASK[0:3]
The RQ Compare Value and the RQ Compare Mask enable traps on specific transactions. A hit to the RQ Compare is
determined by hit = (RQ_IN & RQ_COMPARE_MASK) == RQ_COMPARE_VAL). A hit can trigger the RQ_CMP error
sources when they are enabled. The value is compared only after the packet is arbitrated.
Request Compare Mask (RQ_COMPARE_MASK[0])
Request Compare Mask (RQ_COMPARE_MASK[1])
Request Compare Mask (RQ_COMPARE_MASK[2])
Request Compare Mask (RQ_COMPARE_MASK[3])
MSR Address GLIU0: 100000C1h
GLIU1: 400000C1h
Typ e R /W
Reset Value 00000000_00000000h
MSR Address GLIU0: 100000C3h
GLIU1: 400000C3h
Typ e R /W
Reset Value 00000000_00000000h
MSR Address GLIU0: 100000C5h
GLIU1: 400000C5h
Type R /W
Reset Value 00000000_00000000h
MSR Address GLIU0: 100000C7h
GLIU1: 400000C7h
Type R /W
Reset Value 00000000_00000000h
RQ_COMPARE_MASK[0:3] Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD RQ_MASK
313029282726252423222120191817161514131211109876543210
RQ_MASK
RQ_COMPARE_MASK[0:3] Bit Descriptions
Bit Name Description
63:53 RSVD Reserved.
52:0 RQ_MASK Request Packet Mask. This field is bit-wise logically ANDed with the incoming request
packet before it is compared to the RQ_COMPVAL.