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AMD Geode™ LX Processors Data Book 137
CPU Core Register Descriptions
33234H
5.5.2.30 Extended Debug Registers 1 and 0 MSR (XDR1_XDR0_MSR)
XDR1/XDR0_MSR provides access to Extended Debug Register 1 (XDR1) and Extended Debug Register 0 (XDR0). XDR0
and XDR1 each contain either an I/O port number or a linear address for use as an extended breakpoint.
5.5.2.31 Extended Debug Registers 3 and 2 MSR (XDR3_XDR2_MSR)
XDR3/XDR2_MSR provides access to Extended Debug Register 3 (XDR3) and Extended Debug Register 2 (XDR2). XDR2
and XDR3 each contain either an I/O port number or a linear address for use as an extended breakpoint.
MSR Address 00001350h
Typ e R /W
Reset Value 00000000_00000000h
XDR1_XDR0_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
XDR1
313029282726252423222120191817161514131211109876543210
XDR0
XDR1_XDR0_MSR Bit Descriptions
Bit Name Description
63:32 XDR1 Extended Breakpoint 1 I/O Port Number/Linear Address.
31:0 XDR0 Extended Breakpoint 0 I/O Port Number/Linear Address.
MSR Address 00001351h
Typ e R /W
Reset Value 00000000_00000000h
XDR3_XDR2_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
XDR3
313029282726252423222120191817161514131211109876543210
XDR2
XDR3_XDR2_MSR Bit Descriptions
Bit Name Description
63:32 XDR3 Extended Breakpoint 3 I/O Port Number/Linear Address.
31:0 XDR2 Extended Breakpoint 2 I/O Port Number/Linear Address.