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62 AMD Geode™ LX Processors Data Book
GLIU Register Descriptions
33234H
4.2.2.3 Arbitration (ARB)
4.2.2.4 Asynchronous SMI (ASMI)
ASMI is a condensed version of the port ASMI signals. The MASK bits can be used to prevent a device from issuing an
ASMI. If the MASK = 1, the device’s ASMI is disabled.
MSR Address GLIU0: 10000082h
GLIU1: 40000082h
Typ e R /W
Reset Value 10000000_00000000h
ARB Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
QUACK_EN
PIPE_DIS
RSVD
DACK_EN
RSVD
313029282726252423222120191817161514131211109876543210
RSVD
ARB Bit Descriptions
Bit Name Description
63 QUACK_EN Quadruple Acknowledge Enabled. Allow four acknowledgements in a row before
advancing round-robin arbitration. Only applies when arbitrating matching priorities.
0: Disable.
1: Enable.
62 PIPE_DIS Pipelined Arbitration Disabled.
0: Pipelined arbitration enabled and GLIU is not limited to one outstanding transaction.
1: Limit the entire GLIU to one outstanding transaction.
61 RSVD Reserved.
60 DACK_EN Double Acknowledge Enabled. Allow two acknowledgements in a row before advanc-
ing round-robin arbitration. Only applies when arbitrating matching priorities.
0: Disable.
1: Enable.
59:0 RSVD Reserved.
MSR Address GLIU0: 10000083h
GLIU1: 40000083h
Typ e R /W
Reset Value 00000000_00000000h
ASMI Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
ASMI_MASK7
ASMI_MASK6
ASMI_MASK5
ASMI_MASK4
ASMI_MASK3
ASMI_MASK2
ASMI_MASK1
ASMI_MASK0
ASMI_FLAG7
ASMI_FLAG6
ASMI_FLAG5
ASMI_FLAG4
ASMI_FLAG3
ASMI_FLAG2
ASMI_FLAG1
ASMI_FLAG0