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AMD Geode™ LX Processors Data Book 355
Display Controller Register Descriptions
33234H
6.6.16 VGA Block Configuration Registers
6.6.16.1 VGA Configuration (VGA_CONFIG)
This register controls palette write operations.
6.6.16.2 VGA Status (VGA_STATUS)
This register provides status information for the individual SMI events enabled in the VGA_CONFIG register (DC Memory
Offset 100h), as well as certain other status bits. Reading this register clears all active events.
DC Memory Offset 100h
Typ e R /W
Reset Value 00000000h
VGA_CONFIG Register Map
313029282726252423222120191817161514131211109876543210
RSVD
WPPAL
VGA_CONFIG Bit Descriptions
Bit Name Description
31:1 RSVD Reserved. Set to 0.
0 WPPAL Write Protect Palette. If set to 1, VGA palette write operations are NOT written to the
palette RAMs. Palette writes behave normally, except that the data is discarded.
DC Memory Offset 104h
Typ e RO
Reset Value 00000000h
VGA_STATUS Register Map
313029282726252423222120191817161514131211109876543210
RSVD BLINK_CNT RSVD V_CNT RSVD
VSYNC
DISPEN
CRTCIO_SMI
VBLANK_SMI
ISR0_SMI
MISC_SMI
VGA_STATUS Bit Descriptions
Bit Name Description
31:30 RSVD Reserved.
29:24 BLINK_CNT Blink Counter Value. Unsynchronized, used as a simulation aid.
23:22 RSVD Reserved.
21:12 V_CNT Vertical Counter Value. Unsynchronized, used as a simulation aid.
11:6 RSVD Reserved.
5 VSYNC VSYNC. 1 If VSYNC is active (copy of bit 3 of ISR1).
4DISPEN Display Enable. 0 if both horizontal and vertical display enable are active (copy of bit 0
of ISR1).
3 CRTCIO_SMI CRTC Register SMI. If = 1, an SMI was generated due to an I/O read or write to an non-
implemented CRTC register.