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4–16 Cache and External Interfaces
21264/EV68A Hardware Reference Manual
System Port
If the ChangeToDirty command succeeds, the STx_C enters the writable state, and the
Mbox locks the Dcache line. The Mbox does not release the Dcache line until the
STx_C data is transferred to the Dcache. This ensures that no other agent, by way of a
probe, can take the block before the STx_C can update the locked block.
4.6.4 Managing Speculative Store Issues with Multiprocessor Systems
The 21264/EV68A provides two mechanisms to manage an inherent potential side
effect of speculative execution with multiprocessor systems — a livelock condition
caused by a speculative store that misses in one processor affecting the execution of a
LDx_L/STx_C pair in another processor. The potential livelock condition in multipro-
cessor systems can be effectively controlled by placing processors in a conservative
mode, where speculative store MAFs are blocked. The 21264/EV68A manages conser-
vative mode with the Mbox IPR, M_CTL[SMC], described in Table 5–19.
• M_CTL[SMC] can be set to place the 21264/EV68A in full-time conservative
mode.
• M_CTL[SMC] can be set to place the 21264/EV68A in periodic conservative
mode, timed by two counters: an 8-bit primary counter that tracks branch mispre-
dicts and conditional branch retires, and a backup counter that places the 21264/
EV68A in conservative mode for a period of 16K cycles every 2 million cycles.
The 8-bit counter is enabled by placing M_CTL[SMC] in periodic conservative
mode. The backup counter takes effect whenever the 8-bit counter is enabled. Fur-
ther, the backup counter can be reset to 0 by clearing a previously set
M_CTL[SMC], allowing synchronization between processors.
4.7 System Port
The system port is the 21264/EV68A’s connection to either a memory or I/O controller
or to a shared multiprocessor system controller. System port interface signals are shown
in Figure 4–4.
The system port supports transactions between the 21264/EV68A and the system. Sys-
tems must receive and drive signals that are asserted low. Transaction commands are
communicated on signal lines SysAddOut_L[14:0] (21264/EV68A-to-system) and
SysAddIn_L[14:0] (system-to-21264/EV68A). Transaction data is transferred on a
bidirectional data bus over pins SysData_L[63:0] with ECC on pins SysCheck_L[7:0].