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21264/EV68A Hardware Reference Manual
Testability and Diagnostics 11–5
Power-Up Self-Test and Initialization
Figure 11–1 TestStat_H Pin Timing During Power-Up Built-In Self-Test (BiST)
Figure 11–2 TestStat_H Pin Timing During Built-In Self-Initialization (BiSI)
11.5 Power-Up Self-Test and Initialization
Upon powering up, the 21264/EV68A automatically performs the self-test of all major
embedded RAM arrays and then loads the Cbox configuration registers and the instruc-
tion cache from the system SROM. The chip’s internal logic is held in reset during
these operations. See Chapter 9 for sequencing of power-up operations.
11.5.1 Built-in Self-Test
The power-up self-test is performed on the instruction cache and tag arrays, the data
cache and tag arrays, the triplicate tag arrays, and the various RAM arrays located in the
branch history table logic. The power-up self-test lasts for approximately 700,000 CPU
cycles. The result of self-test is made available as Pass/Fail status on the TestStat_H
pin (see Section 11.4).
The result of self-test is also available in an IPR bit. Software can read this status
through IPR I_CTL(23) (0 = pass, 1 = fail). See Section 5.2.15.
The power-up BiST leaves all bits in all arrays initialized to zeroes. The instruction
cache and the tag are reinitialized as part of the SROM initialization step. This is
detailed in Section 11.5.2.
11.5.2 SROM Initialization
Power-up initialization on the 21264/EV68A is different from previous generation
Alpha systems in two aspects. First, in the 21264/EV68A systems, the presence of
serial ROMs is mandatory as initialization of several Cbox configuration registers
depends on them. Second, it is possible to skip or partially fill Icache from serial
ROMs. Figure 11–3 shows the map of the data in serial ROMs.
BiSTResult
ClkFwdReset_L
Tbox_Reset_A_L
TBox Reset Engine
TestStatus_H
DoBistIdle DoResult DoSROM Idle
LKG-10950A-98WF
BiSTResult OR T
TimeOut
ClkFwdRst_L1
Tbox_Rst_A_L1
TBox Reset Engine1
TestStatus_H1
DoMfgSelfinitIdle Idle
LKG-10951A-98WF