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21264/EV68A Hardware Reference Manual
PQFP
Plastic quad flat pack.
primary cache
The cache that is the fastest and closest to the processor. The first-level caches, located
on the CPU chip, composed of the Dcache and Icache.
program counter
That portion of the CPU that contains the virtual address of the next instruction to be
executed. Most current CPUs implement the program counter (PC) as a register. This
register may be visible to the programmer through the instruction set.
PROM
Programmable read-only memory.
pull-down resistor
A resistor placed between a signal line and a negative voltage.
pull-up resistor
A resistor placed between a signal line to a positive voltage.
QNaN
Quiet Nan. See NaN.
quad issue
Four instructions are issued, in parallel, during the same microprocessor cycle. The
instructions use different resources and so do not conflict.
quadword
Eight contiguous bytes starting on an arbitrary byte boundary. The bits are numbered
from right to left, 0 through 63.
RAM
Random-access memory.
RAS
Row address select.
RAW
Read-after-write.
READ_BLOCK
A transaction where the 21264/EV68A requests that an external logic unit fetch read
data.
read data wrapping
System feature that reduces apparent memory latency by allowing read data cycles to
differ the usual low-to-high sequence. Requires cooperation between the 21264/EV68A
and external hardware.