Compaq 21264 Network Card User Manual


 
2–2 Internal Architecture
21264/EV68A Hardware Reference Manual
21264/EV68A Microarchitecture
Floating-point execution unit (Fbox)
Onchip caches (Icache and Dcache)
Memory reference unit (Mbox)
External cache and system interface unit (Cbox)
Pipeline operation sequence
2.1.1 Instruction Fetch, Issue, and Retire Unit
The instruction fetch, issue, and retire unit (Ibox) consists of the following subsections:
Virtual program counter logic
Branch predictor
Instruction-stream translation buffer (ITB)
Instruction fetch logic
Register rename maps
Integer and floating-point issue queues
Exception and interrupt logic
Retire logic
2.1.1.1 Virtual Program Counter Logic
The virtual program counter (VPC) logic maintains the virtual addresses for instruc-
tions that are in flight. There can be up to 80 instructions, in 20 successive fetch slots, in
flight between the register rename mappers and the end of the pipeline. The VPC logic
contains a 20-entry table to store these fetched VPC addresses.