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21264/EV68A Hardware Reference Manual
Internal Processor Registers 5–35
Cbox CSRs and IPRs
BC_WR_RD_BUBBLES[0:3] Write to read GCLK bubbles.
DUP_TAG_ENABLE Duplicate CSR.
SKEWED_FILL_MODE Duplicate CSR.
BC_RDVICTIM Duplicate CSR.
SKEWED_FILL_MODE Duplicate CSR.
BC_RDVICTIM Duplicate CSR.
BC_CLEAN_VICTIM Duplicate CSR.
DUP_TAG_MODE Duplicate CSR.
SKEWED_FILL_MODE Duplicate CSR.
ENABLE_PROBE_CHECK Enable error checking during probe processing.
SPEC_READ_ENABLE[0] Enable speculative references to the system port.
SKEWED_FILL_MODE Duplicate CSR.
SKEWED_FILL_MODE Duplicate CSR.
MBOX_BC_PRB_STALL Must be asserted when BC_RATIO = 4.0X, 5.0X, 6.0X, 7.0X, or
8.0X.
BC_LAT_DATA_PATTERN[0:31] Bcache data latency pattern.
BC_LAT_TAG_PATTERN[0:23] Bcache tag latency pattern.
BC_RDVICTIM Duplicate CSR.
ENABLE_STC_COMMAND[0] Enable STx_C instructions to the pins.
BC_LATE_WRITE_NUM[0:2] Number of Bcache clocks to delay the data for Bcache write com-
mands.
BC_CPU_LATE_WRITE_NUM[0:1] Number of GCLK cycles to delay the Bcache clock/data from
index.
BC_BURST_MODE_ENABLE[0] Burst mode enable signal.
BC_PENTIUM_MODE[0] Enable Pentium mode RAM behavior.
BC_CLK_RATIO[1] Duplicate CSR.
BC_FRM_CLK[0] Force all Bcache transactions to start on rising edges of the A phase
of a GCLK.
BC_CLK_DELAY[0:1] Delay of Bcache clock for 0,0,1,2 GCLK phases.
BC_DDMR_ENABLE[0] Enables the rising edge of the Bcache forwarded clock (always
enabled).
BC_DDMF_ENABLE[0] Enable the falling edge of the Bcache forwarded clock. (always
enabled).
BC_LATE_WRITE_UPPER[0] Asserted when (BC_LATE_WRITE_NUM > 3) or
((BC_LATE_WRITE_NUM = 3) and
(BC_CPU_LATE_WRITE_NUM > 1)).
Table 5–24 Cbox WRITE_ONCE Chain Order (Continued)
Cbox WRITE_ONCE Chain Description